module MFUNC_TOP ( /*AUTOARG*/
   // Outputs
   reg_MFUNC_TOP_rd_data, params_start, params_ch0_start,
   params_ch1_start, params_ch2_start, params_ch3_start,
   params_saddr_l, params_saddr_h, params_daddr_l, params_daddr_h,
   params_data_len, params_wr_mode, params_rd_mode, params_test,
   // Inputs
   clk, rst_n, reg_MFUNC_TOP_wr_en, sub_reg_addr, reg_wr_data,
   params_data_done, params_test_ro
   );
input         clk;
input         rst_n;
input         reg_MFUNC_TOP_wr_en;
input  [ 7:0] sub_reg_addr;
input  [ 7:0] reg_wr_data;
output [ 7:0] reg_MFUNC_TOP_rd_data;
output  [1:0]   params_start;
output  [0:0]   params_ch0_start;
output  [1:0]   params_ch1_start;
output  [1:0]   params_ch2_start;
output  [0:0]   params_ch3_start;
output  [7:0]   params_saddr_l;
output  [7:0]   params_saddr_h;
output  [7:0]   params_daddr_l;
output  [7:0]   params_daddr_h;
output  [7:0]   params_data_len;
output           params_wr_mode;
output           params_rd_mode;
input            params_data_done;
output  [15:0]   params_test;
input   [15:0]   params_test_ro;
/////////////////////////////////////////////////////
reg  [ 7:0]   reg_MFUNC_TOP_rd_data;
reg  [7:0]   reg_00;
reg  [7:0]   reg_01;
reg  [7:0]   reg_02;
reg  [7:0]   reg_03;
reg  [7:0]   reg_04;
reg  [7:0]   reg_05;
reg           reg_06;
reg           reg_07;
reg           reg_08;
reg  [7:0]   reg_09;
reg  [7:0]   reg_0a;
reg  [7:0]   reg_0b;
reg  [7:0]   reg_0c;
wire          wr_00_en;
wire          wr_01_en;
wire          wr_02_en;
wire          wr_03_en;
wire          wr_04_en;
wire          wr_05_en;
wire          wr_06_en;
wire          wr_07_en;
wire          wr_08_en;
wire          wr_09_en;
wire          wr_0a_en;
wire          wr_0b_en;
wire          wr_0c_en;
assign          wr_00_en=(reg_MFUNC_TOP_wr_en&&(sub_reg_addr==8'h00));
assign          wr_01_en=(reg_MFUNC_TOP_wr_en&&(sub_reg_addr==8'h01));
assign          wr_02_en=(reg_MFUNC_TOP_wr_en&&(sub_reg_addr==8'h02));
assign          wr_03_en=(reg_MFUNC_TOP_wr_en&&(sub_reg_addr==8'h03));
assign          wr_04_en=(reg_MFUNC_TOP_wr_en&&(sub_reg_addr==8'h04));
assign          wr_05_en=(reg_MFUNC_TOP_wr_en&&(sub_reg_addr==8'h05));
assign          wr_06_en=(reg_MFUNC_TOP_wr_en&&(sub_reg_addr==8'h06));
assign          wr_07_en=(reg_MFUNC_TOP_wr_en&&(sub_reg_addr==8'h07));
assign          wr_08_en=(reg_MFUNC_TOP_wr_en&&(sub_reg_addr==8'h08));
assign          wr_09_en=(reg_MFUNC_TOP_wr_en&&(sub_reg_addr==8'h09));
assign          wr_0a_en=(reg_MFUNC_TOP_wr_en&&(sub_reg_addr==8'h0a));
assign          wr_0b_en=(reg_MFUNC_TOP_wr_en&&(sub_reg_addr==8'h0b));
assign          wr_0c_en=(reg_MFUNC_TOP_wr_en&&(sub_reg_addr==8'h0c));
/////////////////////////////////////////////////////
always @(posedge clk or negedge rst_n)
begin
    if (~rst_n) begin
       reg_00<=8'd0;
    end
    else if (wr_00_en) begin
       reg_00<=reg_wr_data;
    end
end
assign  params_start=reg_00[1:0];
assign  params_ch0_start=reg_00[2];
assign  params_ch1_start=reg_00[4:3];
assign  params_ch2_start=reg_00[6:5];
assign  params_ch3_start=reg_00[7];
always @(posedge clk or negedge rst_n)
begin
    if (~rst_n) begin
       reg_01<=8'h00;
    end
    else if (wr_01_en) begin
       reg_01<=reg_wr_data;
    end
end
assign  params_saddr_l=reg_01;
always @(posedge clk or negedge rst_n)
begin
    if (~rst_n) begin
       reg_02<=8'h00;
    end
    else if (wr_02_en) begin
       reg_02<=reg_wr_data;
    end
end
assign  params_saddr_h=reg_02;
always @(posedge clk or negedge rst_n)
begin
    if (~rst_n) begin
       reg_03<=8'h00;
    end
    else if (wr_03_en) begin
       reg_03<=reg_wr_data;
    end
end
assign  params_daddr_l=reg_03;
always @(posedge clk or negedge rst_n)
begin
    if (~rst_n) begin
       reg_04<=8'h00;
    end
    else if (wr_04_en) begin
       reg_04<=reg_wr_data;
    end
end
assign  params_daddr_h=reg_04;
always @(posedge clk or negedge rst_n)
begin
    if (~rst_n) begin
       reg_05<=8'h01;
    end
    else if (wr_05_en) begin
       reg_05<=reg_wr_data;
    end
end
assign  params_data_len=reg_05;
always @(posedge clk or negedge rst_n)
begin
    if (~rst_n) begin
       reg_06<=1'd0;
    end
    else if (wr_06_en) begin
       reg_06<=reg_wr_data;
    end
end
assign  params_wr_mode=reg_06;
always @(posedge clk or negedge rst_n)
begin
    if (~rst_n) begin
       reg_07<=1'd0;
    end
    else if (wr_07_en) begin
       reg_07<=reg_wr_data;
    end
end
assign  params_rd_mode=reg_07;
always @(posedge clk or negedge rst_n)
begin
    if (~rst_n) begin
       reg_08<=1'd0;
    end
    else  begin
       reg_08<=params_data_done;
    end
end
always @(posedge clk or negedge rst_n)
begin
    if (~rst_n) begin
       reg_09<=8'h09;
    end
    else if (wr_09_en) begin
       reg_09<=reg_wr_data;
    end
end
assign  params_test[7:0]=reg_09;
always @(posedge clk or negedge rst_n)
begin
    if (~rst_n) begin
       reg_0a<=8'h0a;
    end
    else if (wr_0a_en) begin
       reg_0a<=reg_wr_data;
    end
end
assign  params_test[15:8]=reg_0a;
always @(posedge clk or negedge rst_n)
begin
    if (~rst_n) begin
       reg_0b<=8'h0b;
    end
    else  begin
       reg_0b<=params_test_ro[7:0];
    end
end
always @(posedge clk or negedge rst_n)
begin
    if (~rst_n) begin
       reg_0c<=8'h0c;
    end
    else  begin
       reg_0c<=params_test_ro[15:8];
    end
end
always @( * )
begin
    case(sub_reg_addr) 
    8'h00 : reg_MFUNC_TOP_rd_data=reg_00;
    8'h01 : reg_MFUNC_TOP_rd_data=reg_01;
    8'h02 : reg_MFUNC_TOP_rd_data=reg_02;
    8'h03 : reg_MFUNC_TOP_rd_data=reg_03;
    8'h04 : reg_MFUNC_TOP_rd_data=reg_04;
    8'h05 : reg_MFUNC_TOP_rd_data=reg_05;
    8'h06 : reg_MFUNC_TOP_rd_data=reg_06;
    8'h07 : reg_MFUNC_TOP_rd_data=reg_07;
    8'h08 : reg_MFUNC_TOP_rd_data=reg_08;
    8'h09 : reg_MFUNC_TOP_rd_data=reg_09;
    8'h0a : reg_MFUNC_TOP_rd_data=reg_0a;
    8'h0b : reg_MFUNC_TOP_rd_data=reg_0b;
    8'h0c : reg_MFUNC_TOP_rd_data=reg_0c;
    default : reg_MFUNC_TOP_rd_data=8'h5a;
    endcase
end
endmodule
